\doxysection{TTCAN\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_t_t_c_a_n___type_def}{}\label{struct_t_t_c_a_n___type_def}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}}


TTFD Controller Area Network.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_aff11e9728333868ba4eee8d96bd7b1d1}{TTTMC}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_acc58286abc6cb0a409cc5c8346e80b80}{TTRMC}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a481228de486ce6fe4960b9709d0c90c9}{TTOCF}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a0dc5f9c6576e671ec4ed4cbb214db8f8}{TTMLM}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a152d9146b25b1589930168b850e2e035}{TURCF}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_adebe813b35b0252f726c512dec2205e1}{TTOCN}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_ad1333598000565e67ce606ab4df12349}{TTGTP}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a2f5146e4240955a51176cff83474cc88}{TTTMK}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a6b78154546d3ed2f8bf410e82f19728e}{TTIR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_ab6582914afd44d63dcbe34c86d597f87}{TTIE}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_ad6b6f7efcb8270de90d47c72f5f78790}{TTILS}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_aafb6b4c57184b25dac3942a0b7623ddb}{TTOST}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a6f375f5f86f7ba5bd97b0065f5e6faa0}{TURNA}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a2b01e8f858a53097cb01738566b6221f}{TTLGT}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a41ef32b487274b09b58f2f1aa0ac2fb8}{TTCTC}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_ab3c55cd5311babe17ea11fc1b8e35141}{TTCPT}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a3bfd0b7f1b6f93b8cbc15c0239a7067d}{TTCSM}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_a07ab626ea35ee4ee72cd659a1c21e691}{RESERVED1}} \mbox{[}111\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_t_c_a_n___type_def_ac3d3333f60663bcd27a9d158b1514b8e}{TTTS}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
TTFD Controller Area Network. 

\label{doc-variable-members}
\Hypertarget{struct_t_t_c_a_n___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_t_t_c_a_n___type_def_a07ab626ea35ee4ee72cd659a1c21e691}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a07ab626ea35ee4ee72cd659a1c21e691} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+RESERVED1\mbox{[}111\mbox{]}}

Reserved, 0x144 -\/ 0x2\+FC \Hypertarget{struct_t_t_c_a_n___type_def_ab3c55cd5311babe17ea11fc1b8e35141}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTCPT@{TTCPT}}
\index{TTCPT@{TTCPT}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTCPT}{TTCPT}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_ab3c55cd5311babe17ea11fc1b8e35141} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTCPT}

TT Capture Time register, Address offset\+: 0x13C \Hypertarget{struct_t_t_c_a_n___type_def_a3bfd0b7f1b6f93b8cbc15c0239a7067d}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTCSM@{TTCSM}}
\index{TTCSM@{TTCSM}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTCSM}{TTCSM}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a3bfd0b7f1b6f93b8cbc15c0239a7067d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTCSM}

TT Cycle Sync Mark register, Address offset\+: 0x140 \Hypertarget{struct_t_t_c_a_n___type_def_a41ef32b487274b09b58f2f1aa0ac2fb8}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTCTC@{TTCTC}}
\index{TTCTC@{TTCTC}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTCTC}{TTCTC}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a41ef32b487274b09b58f2f1aa0ac2fb8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTCTC}

TT Cycle Time and Count register, Address offset\+: 0x138 \Hypertarget{struct_t_t_c_a_n___type_def_ad1333598000565e67ce606ab4df12349}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTGTP@{TTGTP}}
\index{TTGTP@{TTGTP}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTGTP}{TTGTP}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_ad1333598000565e67ce606ab4df12349} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTGTP}

TT Global Time Preset register, Address offset\+: 0x118 \Hypertarget{struct_t_t_c_a_n___type_def_ab6582914afd44d63dcbe34c86d597f87}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTIE@{TTIE}}
\index{TTIE@{TTIE}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTIE}{TTIE}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_ab6582914afd44d63dcbe34c86d597f87} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTIE}

TT Interrupt Enable register, Address offset\+: 0x124 \Hypertarget{struct_t_t_c_a_n___type_def_ad6b6f7efcb8270de90d47c72f5f78790}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTILS@{TTILS}}
\index{TTILS@{TTILS}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTILS}{TTILS}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_ad6b6f7efcb8270de90d47c72f5f78790} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTILS}

TT Interrupt Line Select register, Address offset\+: 0x128 \Hypertarget{struct_t_t_c_a_n___type_def_a6b78154546d3ed2f8bf410e82f19728e}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTIR@{TTIR}}
\index{TTIR@{TTIR}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTIR}{TTIR}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a6b78154546d3ed2f8bf410e82f19728e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTIR}

TT Interrupt register, Address offset\+: 0x120 \Hypertarget{struct_t_t_c_a_n___type_def_a2b01e8f858a53097cb01738566b6221f}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTLGT@{TTLGT}}
\index{TTLGT@{TTLGT}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTLGT}{TTLGT}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a2b01e8f858a53097cb01738566b6221f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTLGT}

TT Local and Global Time register, Address offset\+: 0x134 \Hypertarget{struct_t_t_c_a_n___type_def_a0dc5f9c6576e671ec4ed4cbb214db8f8}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTMLM@{TTMLM}}
\index{TTMLM@{TTMLM}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTMLM}{TTMLM}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a0dc5f9c6576e671ec4ed4cbb214db8f8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTMLM}

TT Matrix Limits register, Address offset\+: 0x10C \Hypertarget{struct_t_t_c_a_n___type_def_a481228de486ce6fe4960b9709d0c90c9}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTOCF@{TTOCF}}
\index{TTOCF@{TTOCF}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTOCF}{TTOCF}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a481228de486ce6fe4960b9709d0c90c9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTOCF}

TT Operation Configuration register, Address offset\+: 0x108 \Hypertarget{struct_t_t_c_a_n___type_def_adebe813b35b0252f726c512dec2205e1}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTOCN@{TTOCN}}
\index{TTOCN@{TTOCN}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTOCN}{TTOCN}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_adebe813b35b0252f726c512dec2205e1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTOCN}

TT Operation Control register, Address offset\+: 0x114 \Hypertarget{struct_t_t_c_a_n___type_def_aafb6b4c57184b25dac3942a0b7623ddb}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTOST@{TTOST}}
\index{TTOST@{TTOST}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTOST}{TTOST}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_aafb6b4c57184b25dac3942a0b7623ddb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTOST}

TT Operation Status register, Address offset\+: 0x12C \Hypertarget{struct_t_t_c_a_n___type_def_acc58286abc6cb0a409cc5c8346e80b80}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTRMC@{TTRMC}}
\index{TTRMC@{TTRMC}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTRMC}{TTRMC}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_acc58286abc6cb0a409cc5c8346e80b80} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTRMC}

TT Reference Message Configuration register, Address offset\+: 0x104 \Hypertarget{struct_t_t_c_a_n___type_def_aff11e9728333868ba4eee8d96bd7b1d1}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTTMC@{TTTMC}}
\index{TTTMC@{TTTMC}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTTMC}{TTTMC}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_aff11e9728333868ba4eee8d96bd7b1d1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTTMC}

TT Trigger Memory Configuration register, Address offset\+: 0x100 \Hypertarget{struct_t_t_c_a_n___type_def_a2f5146e4240955a51176cff83474cc88}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTTMK@{TTTMK}}
\index{TTTMK@{TTTMK}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTTMK}{TTTMK}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a2f5146e4240955a51176cff83474cc88} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTTMK}

TT Time Mark register, Address offset\+: 0x11C \Hypertarget{struct_t_t_c_a_n___type_def_ac3d3333f60663bcd27a9d158b1514b8e}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TTTS@{TTTS}}
\index{TTTS@{TTTS}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TTTS}{TTTS}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_ac3d3333f60663bcd27a9d158b1514b8e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TTTS}

TT Trigger Select register, Address offset\+: 0x300 \Hypertarget{struct_t_t_c_a_n___type_def_a152d9146b25b1589930168b850e2e035}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TURCF@{TURCF}}
\index{TURCF@{TURCF}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TURCF}{TURCF}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a152d9146b25b1589930168b850e2e035} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TURCF}

TUR Configuration register, Address offset\+: 0x110 \Hypertarget{struct_t_t_c_a_n___type_def_a6f375f5f86f7ba5bd97b0065f5e6faa0}\index{TTCAN\_TypeDef@{TTCAN\_TypeDef}!TURNA@{TURNA}}
\index{TURNA@{TURNA}!TTCAN\_TypeDef@{TTCAN\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TURNA}{TURNA}}
{\footnotesize\ttfamily \label{struct_t_t_c_a_n___type_def_a6f375f5f86f7ba5bd97b0065f5e6faa0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TTCAN\+\_\+\+Type\+Def\+::\+TURNA}

TT TUR Numerator Actual register, Address offset\+: 0x130 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
